FIG. 1 is a sectional view of a conventional heterojunction FET. On a semi-insulating GaAs substrate 11, the following layers are deposited to form a heterojunction FET: a nondoped GaAs layer 12 serving as a channel layer, an n-AlGaAs layer 13 serving as an electron supply layer, an n.sup.+ -GaAs layer 15 for providing an ohmic contact that is heavily doped with Si, a gate electrode 16 forming a Schottky junction with the n-AlGaAs layer 13, and source and drain electrodes 17, 18.
FIG. 2 is a sectional view of another conventional heterojunction FET. The basic device structure is the same as in FIG. 1, but an n-GaAs layer 14 is formed on the n-AlGaAs layer 13, having the gate 16, source 17, and drain 18 formed thereon.
In such heterojunction FETs, a two-dimensional electron gas (hereinafter referred to as 2-DEG) 19 is generated in the non-doped GaAs layer 12 near the interface of the n-AlGaAs layer 13. Since the mobility of 2-DEG 19 is not reduced by impurity scattering, the heterojunction FETs can be provided with a high electron mobility and a mutual conductance (gm) that quickly rises from pinchoff.
The above types of transistor are disclosed in Japanese Patent Application Laid-open No. Sho 63-211770.
In an FET using the 2-DEG 19, when charge control of the 2-DEG 19 is performed by applying a relatively low voltage to the gate, the portion of the electron supply layer (n-AlGaAs layer 13) just under the gate is depleted and no current flows through this layer. Therefore, as shown in FIG. 3A, only 2-DEG current 19a contributes to drain current I.sub.D and gm shows a large value determined by the sheet carrier density n.sub.S of the 2-DEG 19. As the positive voltage, Vg, applied to the gate is higher, the sheet carrier density n.sub.S in the 2-DEG 19 is growing and gm increases accordingly as shown in FIG. 3B.
However, if the gate voltage Vg is further increased, the sheet carrier density n.sub.S reaches a maximum n.sub.SO and the conduction band of the electron supply layer 13 partially flattens to generate carriers. As a result, another current path (parallel conduction 20) occurs in the electron supply layer 13 (FIG. 3A), so that the drain current I.sub.D is given by a sum of the 2-DEG current 19a and a current due to the parallel conduction 20. Therefore, in this case, gm is determined by both the 2-DEG current 19a and the current of the parallel conduction 20. The maximum gm is obtained somewhere around this point.
After the appearance of the flat portion in the conduction band of the electron supply layer, the carrier density in the 2-DEG 19 is kept constant at n.sub.SO and gm is determined only by a current variation in the electron supply layer. Since the electron mobility of the AlGaAs layer 13 where the electron supply layer is formed is smaller than that of the 2-DEG 19 by more than one order, gm decreases steeply as shown in FIG. 3B.
In the conventional FET in FIG. 1, the thickness of the electron supply layer (n-AlGaAs layer 13) is considered only from the viewpoint of the ability to supply electrons to the channel layer. Therefore, the electron supply layer is usually made thick, and is made thinner only to the extent that depletion is obtained at equilibrium. Therefore, as described above, parallel conduction occurs under a high bias voltage condition, resulting in reduction of gm.
On the other hand, the conventional FET as shown in FIG. 2 exhibits a smaller reduction of gm than the FET of FIG. 1. The reason is that, in the FET of FIG. 2, parallel conduction is partly due to the GaAs layer 14, which has a larger electron mobility than the AlGaAs layer 13. However, since the carrier density in the n-GaAs layer 14 is reduced in order to form the Schottky junction, the parallel conduction in the AlGaAs layer 13 becomes dominant under higher bias voltage. Thus, the conventional FETs of FIGS. 1 and 2 have the same basic characteristics of gm-Vg as that shown in FIG. 3B.